This invention relates to an oscillator comprising, connected between a first and a second power supply terminal, a series connection of a current source which is controllable by frequency stabilization means and which is connected to the second power supply terminal and a parallel connection of a capacitive load and a current path of a switching element, which parallel connection is connected to the first power supply terminal, a junction point between the controllable current source and the parallel connection being fed back, via a delay circuit, to a control connection of the switching element.
An oscillator of this kind is known from U.S. Pat. No. 4,015,219. The known oscillator is a ring oscillator comprising cyclically cascaded stages, a stage comprising a series connection of the current paths of a first and a second field effect transistor. The current paths of the first and second transistors are connected to the first and second power supply terminal, respectively. A junction point between the current paths is connected to the gate electrode of the first transistor in the next stage. In all stages but one the junction point is connected to the first power supply terminal via a capacitance. The stage which does not include such a capacitance acts as an output stage. The gate electrode of the second transistors is connected to the frequency stabilization means. The frequency stabilization means comprise a parallel connection of the current paths of a third and a fourth transistor which are connected on the one side to the first power supply terminal and on the other side to the second power supply terminal via a resistor. The gate electrodes of the third and fourth transistors are connected to the second power supply terminal and the first power supply terminal, respectively. The junction point between the parallel connection and the resistor is connected to the gate electrode of each second transistor. The first and the third transistor are substantially identical and of the P-channel enhancement type; the second and the fourth transistor are substantially identical and of the P-channel depletion type. The operation of the known frequency stabilization means is as follows. When the temperature of the circuit rises, the switching threshold of the first transistor, necessary for conducting the current source, increases. Consequently, the charging current decreases and hence the oscillation period increases, because a longer period of time is required for raising the capacitance to a voltage equal to the switching threshold. The impedance of the parallel connection in the frequency stabilization means also increases so that the voltage at the junction point increases. Consequently, the second transistor supplies more current, counteracting the effect of the temperature rise. When the voltage on the second power supply terminal increases, the current through the second transistor increases. This reduces the oscillation period because the voltage across the capacitance increases faster so as to reach the switching threshold sooner. The current through the third transistor, however, also increases, so that the voltage at the junction point causes a decrease of the control voltage for the second transistor and the current therethrough decreases. This counteracts the effect of fluctuations of the power supply voltage.
The known frequency stabilization means must be very accurately proportioned in order to avoid overcompensation or undercompensation. This is due to the fact that, even though the first and the third transistor are substantially identical, like the second and the fourth transistor, the operating ranges of the identical transistors are not interrelated. This can be explained as follows. Each second transistor receives a control voltage which is determined by the voltage drop across the resistor. The voltage drop is caused by the currents through the channels of the third and the fourth transistor. However, the fourth transistor, being substantially identical to the second transistor, receives the voltage of the first power supply terminal on its gate electrode and experiences a driving voltage which is caused by the voltage drop across the resistor.
Each first transistor is controlled by a control voltage which varies, inter alia, in dependence on the number of stages, and on the voltage between the first power supply terminal and the second power supply terminal. Each first transistor then experiences a driving voltage which also changes with a change in the voltage between the power supply terminals. The gate electrode of the third transistor receives the voltage of the second supply terminal. The driving voltage of the third transistor, however, is determined by the voltage drop across the resistor. The first and the second transistor, therefore, operate in a range which deviates from the operating range of the third and the fourth transistor, respectively, so that the setting of the frequency stabilization means is not stable because it is still liable to drift.